1. Field of the Invention
The present invention is directed to the process of reworking pin grid array chip carriers, and more particularly, to the process of reworking pin grid array chip carriers using an electrolytic etch process.
2. Description of the Related Art
Ceramic, glass and glass-ceramic substrates have been widely used in the computer industry as chip carriers, wherein semiconductor integrated circuit chips are attached to the substrate. The chip carriers may be single layer or multilayer and may be also single chip or multichip. A particular kind of chip carrier is called a pin grid array (hereafter PGA) chip carrier wherein input/output (hereafter I/O) pins are used to connect the PGA chip carrier to the next level of packaging, usually a card.
In the manufacturing of a PGA, the I/O pins are brazed to I/O pads on a surface of the PGA chip carrier. Thereafter, the pins are nickel and gold electroplated. During the plating operation, all pins must contact a common electrode, for example the electrically conductive foil disclosed in Canaperi et al. U.S. Pat. No. 5,516,416, the disclosure of which is incorporated by reference herein, to pass current to them and carry on the plating process. A poor contact, or a complete lack of contact, with the electrode results in unplated I/O pins. Unplated I/O pins are unacceptable and must be reworked.
Further, if the gold plating was too thick or too thin on the I/O pins, the I/O pins would also have to be reworked.
It is not feasible to plate pins on a one-by-one basis so it is necessary to rework all the I/O pins.
The following references illustrate the state of the pertinent art.
Layher et al. U.S. Pat. No. 4,914,813, the disclosure of which is incorporated by reference herein, discloses the rebuilding of PGA chip carriers which includes removing the I/O pins and other metallurgy, replating the I/O pads, brazing new I/O pins to the I/O pads and replating the I/O pins with nickel and gold.
Yu et al. U.S. Pat. No. 5,722,579, the disclosure of which is incorporated by reference herein, discloses a method of reworking a PGA chip carrier which includes shearing off the I/O pins, polishing the surface of the PGA chip carrier, laying down new I/O pads and attaching new I/O pins.
A current rework process consists of shearing the I/O pins off, etching of any leftover braze, replating of top and bottom surface metallurgy, pin braze with new pins and plating of the new pins.
Such a process is time consuming and expensive. It would be desirable to have a rework process which is less time consuming and less expensive.
Accordingly, it is a purpose of the present invention to have a process for reworking PGA chip carriers wherein the entire PGA chip carrier does not need to be reworked in order to rework just the I/O pins.
It is another purpose of the present invention to have a process for reworking PGA chip carriers which is less time consuming and less expensive.